RTL Verification Engineer

Job Title, Lab

Contractor Verification Engineer, APL

General Description Vision

Perform pre-silicon validation of GPU unit(s).

Responsibilities Include

• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers.
• Review unit level test plans; modify if necessary.
• Write the tests outlined by test plan. Enhance testbench if necessary, e.g. add coverage assertions.
• Debug test failures, fix test or testbench if necessary. Report RTL failures to RTL designers. Confirm bug is fixed.
• Enhance test benches and tests to achieve coverage goals.
• Support debug of unit in upper levels of design hierarchy.

Experience Requirements

• Has used modern verification methodologies such UVM/VMM/OVM. UVM is preferred.
• Experience verifying and debugging RTL , preferably in context of CPU, GPU, video, display or signal processing system.
• Understanding of micro-architecture and logic design fundamentals, e.g. finite state machines, arithmetic data path pipelines.
• Composed functional coverage assertions, preferably using system Verilog.

The qualified candidate will possess the following

• BSEE or higher degree.
• At least 2 years of industry experience in a design verification role.
• Proficient in System Verilog. C++, Python/Perl skills are also desirable.
• Good verbal and written communication skills.

All your information will be kept confidential according to EEO guidelines.